Timers are well known and employed in a variety of electrical devices, such as for example to provide desired delays (e.g., user-defined delays) and other time-related functions. One drawback of some conventional timers is their limited resolution. For example, a conventional timer may only provide a power-of-2 resolution with respect to the available time intervals.
Another drawback is that a number of conventional timers within an electrical device may share certain common circuitry in such a way that the time intervals provided by the different timers are limited significantly (e.g., available time intervals differ within a limited range of 128:1). Furthermore, a conventional timer operating at a lower portion of its intended range may provide a large timing uncertainty (e.g., fifty percent) between a clock used to drive the timer and an event used to trigger the timer.
One or more of the drawbacks noted above may be attributable to design compromises resulting from a limited number of signals available for configuring a timer (e.g., only fifteen bits permitted to configure four timers within a programmable logic device). Conventional timer architectures that attempt to address these drawbacks may require a large number of additional signals to configure the timer and a great deal of additional circuitry, resulting in significant costs in terms of space and complexity. As a result, there is a need for improved timer architectures.